Fundamentals
Logic Gates & Boolean Algebra
Six symbols are all digital logic is built from.
Fundamentals
CMOS Transistor Basics
An inverter is just two switches that are never on at the same time.
Fundamentals
Latches vs Flip-Flops
Transparent while the clock is high vs snaps shut on the edge.
Fundamentals
Adders, Muxes & Decoders
The Lego bricks combinational logic is assembled from.
Fundamentals
Counters & Shift Registers
Flip-flops chained together become memory with a purpose.
Architecture
PPA Tradeoffs
Faster, lower power, smaller area — pick two, always.
Architecture
AMBA APB — Advanced Peripheral Bus
The bus that doesn't try to be fast — just simple, cheap, and predictable.
Architecture
AMBA AHB — Advanced High-performance Bus
Pipelined enough to hide latency, simple enough to still be one shared bus.
Architecture
AMBA AXI — Advanced eXtensible Interface
Five independent channels, out-of-order completion — built for how modern SoCs actually move data.
RTL
Combinational vs Sequential Logic
Does the circuit have memory, or not?
RTL
Finite State Machines
A circuit that remembers where it is.
RTL
Blocking vs Non-blocking Assignments
= updates immediately. <= updates at the end of the time step.
RTL
Clock Domain Crossing (CDC)
One clock's certainty is another clock's coin flip.
RTL
Q-Channel Protocol (Low-Power Clock Gating Handshake)
Don't just cut the clock — ask first, and wait for a yes.
Low Power
Low Power Design & UPF Basics
Not every part of the chip needs to be on all the time.
Verification
Testbench Architecture
Someone has to generate inputs and check outputs — automatically.
Verification
SystemVerilog Assertions
Say what should never happen — and let the simulator catch it.
Verification
Constrained-Random Verification
Let the computer think of test cases you wouldn't.
Verification
UVM Basics
A standard blueprint so verification engineers don't reinvent the testbench every project.
Verification
Functional Coverage
How do you know when you've tested enough?
Synthesis
Timing Constraints (SDC)
Tell the tool what 'fast enough' means, in writing.
Synthesis
Static vs Dynamic Power
Power leaks even when nothing is switching — and switching costs more power.
Synthesis
Technology Mapping & Cell Libraries
Generic gates become real, specific transistors from the foundry's catalog.
DFT
Scan Chains & ATPG
Turn every flip-flop into a shift register, just for testing.
Physical Design
Power Planning & IR Drop
Even copper has resistance — voltage sags on its way across the chip.
Physical Design
Timing-Driven Placement & Congestion
Where you put things determines whether they can even be wired up.
Timing
Clock Tree & Clock Skew
Does every flip-flop see the clock at the same instant?
Timing
Clock Gating
Don't toggle the clock into logic that isn't doing anything.
Physical Design
Metal Layers & Crosstalk
Wires stack on top of each other — and they whisper to their neighbors.
Physical Design
Antenna Effect
Long wires can accidentally become tiny lightning rods during manufacturing.
Physical Design
DRC vs LVS vs LVC
Can we build it? Does it match? Does it still work the same?
Timing
Setup & Hold Timing
Data must be stable around the clock edge — or it's a coin flip.
Timing
PVT Corners
Your chip has to work in the worst case, not just the typical case.
Timing
False Paths & Multicycle Paths
Not every path in the netlist needs to finish in one clock cycle.
Timing
On-Chip Variation
Even two transistors right next to each other aren't perfectly identical.
Signoff
Mask Layers & Tape-out Checklist
One design, dozens of manufacturing masks.
Signoff
Packaging & Post-Silicon Bring-up
The bare silicon die still needs a way to connect to the outside world.