DigiFlop

= updates immediately. <= updates at the end of the time step.

VLSI Concept · RTL
Blocking vs Non-blocking Assignments
= updates immediately. <= updates at the end of the time step.

Blocking assignments (=) execute sequentially and immediately — used for combinational logic. Non-blocking assignments (<=) schedule the update to happen at the end of the current time step, so every right-hand side is evaluated using old values before any register updates — used for sequential (clocked) logic. Mixing them up is one of the most common sources of simulation-vs-synthesis mismatches.

Rule of thumbUse <= (non-blocking) in clocked always blocks. Use = (blocking) in combinational always blocks.
Why it mattersUsing = in sequential logic can create race conditions and mismatches between simulated and synthesized behavior.
Classic exampleA shift register written with = incorrectly collapses all stages to the same value in one step; written with <= it correctly shifts one stage per clock edge.
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