Mask Layers & Tape-out Checklist

VLSI Concept · Signoff

One design, dozens of manufacturing masks.

GDSII isn't one image — it's a stack of separate mask layers (one per process step: wells, poly, each metal layer, vias, etc.) that the fab exposes one at a time to build the chip up layer by layer on the wafer. Before shipping, teams run a final tape-out checklist covering every discipline.

Typical layer countModern processes can have 40-100+ individual mask layers.

Why it mattersA single wrong or missing mask layer can mean an entire multi-million-dollar wafer run is unusable.

Final gateA formal tape-out review/signoff, often requiring sign-off from design, verification, physical design, and DFT.

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