Setup & Hold Timing

VLSI Concept · Timing

Setup & Hold Timing

Data must be stable around the clock edge — or it's a coin flip.

Setup time is how long the data input must be stable BEFORE the clock edge; hold time is how long it must stay stable AFTER the edge. Violate either and the flip-flop can enter metastability — an unresolved, unpredictable output that can propagate garbage through the chip.

Setup violationData arrives too close to (or after) the clock edge — fixed by speeding up logic or slowing the clock.

Hold violationData changes too soon after the clock edge — fixed by adding delay, not by changing the clock (this is why hold fixes are scarier).

Why it mattersThis is exactly what Static Timing Analysis checks, path by path, before a design can tape out.

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