SystemVerilog Assertions

VLSI Concept · Verification

Say what should never happen — and let the simulator catch it.

Assertions describe expected behavior as a property over time — e.g. "a request must be followed by an acknowledge within 3 cycles." Instead of writing explicit check code, you declare the rule once and the simulator continuously watches for violations, pointing at the exact cycle where something went wrong.

Exampleproperty p; @(posedge clk) req |-> ##[1:3] ack; endproperty

Why it mattersBugs get caught right where they happen instead of downstream as a mysterious wrong output.

Common useBus protocol checking, FIFO overflow/underflow, one-hot state encoding checks.

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