Clock Tree & Clock Skew

VLSI Concept · Timing

Does every flip-flop see the clock at the same instant?

Clock skew is the difference in arrival time of the same clock edge at different flip-flops. An unbalanced clock network — different wire lengths or buffer counts to each flop — causes skew; a carefully balanced tree (built during Clock Tree Synthesis) equalizes path lengths so all flops switch together.

Good vs badBalanced tree → skew near zero. Unbalanced routing → skew that eats directly into timing margin.

Why it mattersSkew adds to or subtracts from setup and hold margin at every flop — enough skew causes the same violations as a slow logic path.

Common mistakeAssuming wire delay is negligible — at advanced nodes, interconnect delay often dominates over gate delay.

Related