On-Chip Variation

VLSI Concept · Timing

On-Chip Variation

Even two transistors right next to each other aren't perfectly identical.

On-Chip Variation accounts for the fact that manufacturing and environmental variation isn't perfectly uniform across a single die — two supposedly identical paths can have slightly different delay. STA applies derates (small percentage adjustments) to path delays to guard against this, on top of the global PVT corners.

DerateLaunch path delay is pessimistically increased, capture path pessimistically decreased (or vice versa).

Why it mattersPVT corners alone assume the whole chip is uniform; OCV protects against the chip not being uniform even within one corner.

AOCV/POCVAdvanced/parametric on-chip variation — more precise, distance- and depth-based derating instead of one flat percentage.

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