AHB (Advanced High-performance Bus) sits a level up from APB: it's built for the on-chip blocks that actually need bandwidth — memory controllers, DMA engines, and higher-speed peripherals — without taking on the full complexity of AXI. The defining feature of AHB is pipelining: the address phase of the next transfer is driven onto the bus during the data phase of the current one, so back-to-back transfers can complete at one per cycle even though only a single address bus and a single data bus exist.
That overlap is controlled by HTRANS, a 2-bit signal with four values: IDLE means no transfer is happening; BUSY means the master wants to continue a burst but needs a cycle to get the next item ready; NONSEQ marks the first beat of any transfer or burst, with an address that can be anything; and SEQ marks every following beat of a burst, with HADDR incrementing (or wrapping) in a way tied to the burst type set at the start.
HBURST[2:0] defines that burst type — SINGLE for a one-beat transfer, INCR for an open-ended incrementing burst, and fixed-length INCR4/INCR8/INCR16 or address-wrapping WRAP4/WRAP8/WRAP16 bursts, which matter enormously for cache-line-aligned transfers where you want the critical word first. HSIZE sets the width of each beat (8, 16, 32, up to 1024 bits in later revisions), and HWRITE sets the direction.
As with APB, a slave that needs more time simply holds HREADY low, stretching the current data phase without disturbing the pipelined address phase sitting behind it; HRESP reports OKAY, ERROR, RETRY or SPLIT. The classic full AHB specification also defines a shared bus with multiple masters and an external arbiter deciding who drives the address/control lines each cycle — genuinely complex to implement correctly.
That complexity is exactly why most designs today use AHB-Lite instead: a single-master subset of the same protocol with no arbitration logic at all, which captures nearly all of AHB's pipelining benefit at a fraction of the implementation cost. In modern high-performance SoCs, AXI has largely taken over the role AHB used to play as the primary system interconnect — but AHB (almost always as AHB-Lite) is still everywhere as the mid-tier bus connecting moderate-bandwidth IP to a bridge down to APB below it, or up to an AXI-based interconnect above it.