Constrained-Random Verification

VLSI Concept · Verification

Let the computer think of test cases you wouldn't.

Instead of hand-writing every test case, constrained-random verification generates thousands of pseudo-random stimulus values that still obey legal constraints (e.g. address must be word-aligned). Combined with coverage tracking, this explores corner cases human engineers would never think to write by hand.

Key idearandomize() with constraints — random but always legal.

Why it mattersComplex designs have far too many input combinations to cover with directed tests alone.

Paired withFunctional coverage — tracking which scenarios have actually been exercised, so you know when to stop.

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