VLSI Concept · Low Power Design
Low Power Design & UPF Basics
Not every part of the chip needs to be on all the time.
Older chips ran everything off one power rail, all the time. Modern SoCs don't, because doing so wastes power two different ways: dynamic power, spent every time a transistor switches, and static (leakage) power, which drains a block even when it's sitting completely idle. At advanced process nodes, leakage alone can be the difference between a phone that lasts a day and one that doesn't.
The fix is to split the chip into independent power domains that can be switched off when a block isn't needed, and to describe exactly how that switching should behave in a side-car file called UPF -- the Unified Power Format -- so every tool in the flow, from synthesis through place-and-route to verification, applies the same power intent automatically.
Power DomainsIndependently switchable regions of the chip, each with its own power gate, instead of one shared rail for everything.
Isolation CellsClamp a powered-down domain's outputs to a fixed safe value, so neighboring always-on logic never sees a floating or glitching signal.
Retention CellsSpecial flip-flops fed by a tiny always-on supply that hold critical state through a power-down, so the domain doesn't have to reboot from scratch on wake-up.
Level ShiftersTranslate a signal's voltage swing as it crosses between domains that run at different supply voltages.
UPF (Unified Power Format)An IEEE 1801 standard file, written alongside the RTL, that declares domains, supply nets, and where isolation, retention, and level-shifting are required -- read by synthesis, P&R, and low-power verification tools alike.
Why it mattersBattery-powered and thermally-constrained chips live or die on getting this right -- it's one of the biggest levers on real-world power, alongside clock gating.