Latches vs Flip-Flops

VLSI Concept · Fundamentals

Transparent while the clock is high vs snaps shut on the edge.

A latch is level-sensitive — while its enable is high, the output continuously follows the input ("transparent"); when it goes low, the last value is held. A flip-flop is edge-triggered — it only samples the input at the instant of a clock edge and holds it for the entire cycle. This is why synchronous design almost exclusively uses flip-flops.

Transparency problemA latch left open (enable high) can let a glitch race straight through combinational logic.

Why it mattersAccidentally inferring a latch instead of a flip-flop from incomplete RTL is one of the most common synthesis warnings — and bugs.

Common fixA flip-flop is really two latches in series (master-slave), which is what makes it edge-triggered instead of level-sensitive.

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