DigiFlop

Two bits in, sum and carry out — the simplest adder there is.

Adds three bits — because a carry-in has to go somewhere.

The half adder's mirror image — difference and borrow instead of sum and carry.

Three-bit subtraction: A, B, and a borrow coming in.

Four full adders, daisy-chained by their carry bits.

Which is bigger — A or B — for a single bit?

Same idea, scaled up to a real bus width.

XOR each bit with its neighbor and the ambiguity disappears.

Undoing the Gray-code conversion, one XOR chain at a time.

One select bit picks between two inputs.

Two select bits, four inputs, one output.

Eight inputs, three select bits, one clean line of Verilog.

One input, routed to exactly one of eight outputs.

Turn a 2-bit code into a one-hot 4-bit output.

Same idea, one more address bit, twice the outputs.

The reverse of a decoder — one active line becomes a binary code.

When more than one input is active, the highest-priority one wins.

Whatever is on D gets copied to Q on the next clock edge.

One input: toggle, or don't.

Set, reset, hold, or toggle — all four combinations, no invalid state.

One control bit decides whether the count climbs or falls.

Counts 0 up to N-1, then wraps back to 0.

Counts in Gray code directly, one bit change per step.

A single 1 bit chases itself around a loop of flip-flops.

Feed back the inverted output, and the sequence doubles in length.

A shift register with just enough feedback to look random.