4-bit Ripple Carry Adder

Verilog Coding Exercise · Combinational I

Four full adders, daisy-chained by their carry bits.

Adds two 4-bit numbers by chaining four full adders, each one's carry-out feeding the next one's carry-in — a classic example of structural (gate/module-instantiation) Verilog.

Why "ripple"Carry has to propagate stage by stage, so the worst-case delay grows with the number of bits.

Good exerciseExtend this to 8 bits and think through how the critical path (the carry chain) changes.