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Prove the RTL actually does what it should.

Chip Design Flow · Functional Verification
Functional Verification
Prove the RTL actually does what it should.

Testbenches simulate the RTL against expected behavior, checking waveforms and using assertions to catch bugs before they become silicon. Verification typically takes more engineering time than writing the RTL itself.

InputsRTL code, test plan
OutputsVerified RTL, coverage & bug reports
Typical toolsSimulators, SystemVerilog assertions (SVA), UVM
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Related

Deep dive: Testbench Architecture Deep dive: SystemVerilog Assertions Deep dive: Constrained-Random Verification Deep dive: UVM Basics Deep dive: Functional Coverage Deep dive: Clock Domain Crossing (CDC)