DigiFlop

Dynamic power is consumed only when transistors actually switch state — it's proportional to switching activity, load capacitance, clock frequency, and the square of supply voltage (P = αCV²f). Static power, or leakage power, is consumed continuously even when the circuit is idle and nothing is switching, because transistors never fully turn off — sub-threshold leakage current flows through them regardless of activity. At older process nodes dynamic power dominated total power, but at modern advanced nodes leakage has grown so significantly that it can rival or even exceed dynamic power, especially for idle or lightly-active blocks, which is exactly why techniques like power gating exist.

Clock gating inserts a gating cell — usually an Integrated Clock Gating (ICG) cell rather than a plain AND gate, to avoid glitches — between the clock network and a block of flip-flops that don't need to toggle this cycle, based on an enable condition. Since a flip-flop only burns dynamic power when its clock actually toggles, gating off unused logic can cut dynamic power on that block by 30-50% or more when it's idle a significant fraction of the time, which describes most blocks in most real designs most of the time. It's one of the highest-value, lowest-risk power optimization techniques available, and modern synthesis tools can often infer clock gating automatically from RTL enable conditions.

Clock gating disables the clock to logic that isn't doing useful work that cycle. Fine-grain gating disables individual flip-flops or small register groups based on a local enable condition; coarse-grain gating disables the clock to an entire functional block or module when it's idle for a longer stretch. The risk of getting it wrong is a functional bug (gating the clock while the block still needs to capture data, silently dropping a cycle) or a timing bug (the gating cell shifting clock arrival enough to create hold violations, as covered in the STA questions above).

Clock gating stops a block's clock from toggling, which eliminates dynamic power but does nothing about leakage — the block's registers and logic still leak current even though they're frozen. Power gating goes further by actually disconnecting a block's supply rail using a power switch (a header or footer transistor), cutting both dynamic AND static/leakage power to nearly zero for that block. The tradeoff is that power gating loses the block's internal state (registers need to be restored on wake-up, sometimes via retention flops that keep a small amount of state alive on an always-on rail) and has real wake-up latency, so it's typically used for blocks that stay idle for long, predictable stretches rather than every idle cycle.

A power domain refers to a region of the design that shares a common power switching/gating control — it can be turned on or off (or put into retention) as a unit, independent of other power domains. A voltage domain refers to a region that operates at a particular supply voltage level, which may or may not be independently switchable. In practice these often coincide, but they're conceptually distinct: you could have two voltage domains at the same voltage level that are still separately power-gate-able for independent power sequencing, or a single power domain that always operates at one fixed voltage with no DVFS at all.

An isolation cell is placed on any signal that crosses from a power domain that can be turned off into a domain that stays on (or into another domain that might be off at a different time), and it clamps that signal to a known, safe value (usually 0 or 1, chosen per-signal) whenever the source domain is powered down. Without isolation, an output from a powered-off domain floats to an undefined/indeterminate value, which can cause spurious switching, contention, or even damage in the downstream always-on logic that's still receiving that signal. Isolation strategy (which value to clamp to, and exactly when isolation enables/disables relative to power sequencing) is one of the core things UPF specifies.

A level shifter converts a signal's voltage swing from one power domain's supply level to another when a signal crosses between domains operating at different voltages — for example, a signal going from a 0.7V low-power core domain into a 1.2V I/O domain. Without a level shifter, a logic '1' from the lower-voltage domain might not register as a valid '1' input threshold in the higher-voltage domain (or, going the other direction, could risk exceeding safe voltage limits on transistors designed for the lower voltage), so any cross-domain signal in a multi-Vdd design needs one, sized and placed according to the exact voltage pair involved.

When a block is power-gated off, its ordinary flip-flops lose their stored state entirely since their supply is cut. A retention flip-flop adds a small shadow latch connected to an always-on power rail that isn't switched off, so critical state can be saved into the shadow latch just before power-down and restored from it on power-up, without needing to reload that state from memory or re-run initialization logic. Only registers whose state genuinely needs to survive a power-down cycle are made retention-capable, since every retention flop costs extra area and the always-on rail routing adds design complexity.

Wake-up latency is the time required for a power-gated domain to go from fully off to fully operational again — it involves ramping the supply rail back up (limited by the power switch network and decoupling capacitance to avoid a damaging inrush current / IR-drop spike), restoring any retained state, and waiting for PLLs/clocks in that domain to relock if they were also shut off. Designers manage it by sizing power switches and staging their turn-on (rather than switching the whole domain on instantaneously, which would cause a huge current spike), and by architecting the power state machine to predict wake-up needs early enough that latency is hidden behind other work wherever possible.

DVFS is a runtime power management technique where a chip's operating voltage and clock frequency are both scaled down together during periods of lower performance demand, and scaled back up when more performance is needed. Because dynamic power scales with the square of voltage but only linearly with frequency, lowering both together yields a roughly cubic reduction in dynamic power for a proportional reduction in performance — far more efficient than reducing frequency alone at a fixed voltage. This requires the design to be verified as functionally correct and timing-clean across every voltage/frequency operating point it supports, adding real complexity to the STA and verification effort.

Standard cell libraries typically offer the same logical cell (say, a 2-input NAND) in multiple threshold-voltage flavors: low-Vt cells switch faster but leak significantly more; high-Vt cells leak much less but switch more slowly. During synthesis and physical design, the tool selectively uses low-Vt cells only on genuinely timing-critical paths (where the speed is needed and worth the leakage cost) and high-Vt cells everywhere else (where the extra speed margin is unused and would just be wasted leakage), giving a much better overall power/performance tradeoff than using one uniform cell library everywhere.

UPF (Unified Power Format, the IEEE 1801 standard) — and its earlier alternative CPF — is a separate specification file describing a design's power architecture: power domains, supply nets, isolation and level-shifter requirements at domain boundaries, retention strategy, and power state tables. Power intent is kept separate from RTL because RTL describes pure logical function, while power intent is a physical/architectural decision layered on top — the same RTL block might be power-gated in one product variant and always-on in another. Keeping them separate lets power-aware synthesis, simulation, and verification tools apply the power architecture consistently without polluting the functional RTL with implementation-specific power switches and isolation cells.

This is exactly what a standardized low-power handshake protocol like Arm's Q-Channel is for. Rather than the power controller blindly gating the IP's clock and hoping nothing was mid-transaction, the IP asserts an active signal whenever it has real work in flight; the controller requests quiescence by dropping a request line; the IP either accepts immediately if it's idle, or denies the request if it's still busy, giving the IP itself — not an external guesser — the authority to decide the safe moment to have its clock stopped. This kind of explicit, standardized handshake is the safe alternative to ad-hoc, design-specific clock-gating control signals.

Reducing unnecessary switching activity through better RTL coding (avoiding redundant toggling, using enable-qualified registers), architectural choices like reducing pipeline width or clock frequency where performance headroom allows, operand isolation (blocking inputs to a datapath, like a multiplier, when its result won't be used that cycle), and multi-voltage/DVFS operation itself, which reduces the V² term in the dynamic power equation directly.

A power domain (voltage island) is a region of the chip that can have its power and/or voltage controlled independently from the rest of the die — so, say, the modem can stay powered while the GPU is fully off. Every boundary between domains that can be at different voltages or power states needs isolation cells (to clamp outputs to a safe value when the driving domain is off), level shifters (to translate signal voltage between domains at different voltages), and often retention registers (to preserve state through a power-down).

An isolation cell clamps a signal to a defined, safe value (0 or 1) when the domain driving it loses power, instead of letting that output float or decay to an undefined value. Without one, a powered-down domain's outputs can float into an indeterminate state that the still-powered domain downstream reads as garbage — potentially triggering spurious logic, extra switching (and power) in the still-on domain, or even functional failures.