VLSI Interview Prep
VLSI Interview Questions — AMBA Bus Protocols (APB / AHB / AXI)
Almost every SoC interconnect question traces back to one of these three protocols — knowing which one fits which job, and why, is what separates a real answer from a memorized one.
APB, AHB, and AXI are the three AMBA bus protocols that show up in nearly every SoC interconnect, each solving a different bandwidth/complexity tradeoff — APB for simple low-bandwidth peripherals, AHB for a single pipelined shared bus, and AXI for high-bandwidth, multi-master, out-of-order interconnects. Interview questions on this topic test whether you understand the handshakes and phases well enough to reason about a bus you’ve never seen before, not just recite channel names. These are the questions candidates report most often, from basic transfer phases through AXI’s out-of-order completion and bridging between protocols.
Q1.What are the main differences between APB, AHB, and AXI, and when would you choose each?
APB is the simplest protocol — non-pipelined, one transfer at a time, designed for low-bandwidth peripherals like UARTs, GPIO, and configuration registers where speed doesn't matter but gate count and timing simplicity do. AHB is pipelined (the address phase of the next transfer overlaps the data phase of the current one), giving much higher throughput on a single shared address/data bus, and is used for moderate-bandwidth blocks like DMA controllers or memory-mapped peripherals that need more performance than APB but don't need full AXI complexity. AXI is the high-performance choice — five independent channels (read/write address, read/write data, write response) with out-of-order completion via transaction IDs — used as the primary system interconnect protocol connecting CPUs, caches, and high-bandwidth memory controllers in virtually every modern SoC.
Q2.Walk through the three phases of an APB transfer.
An APB transfer moves through IDLE, SETUP, and ACCESS states, never overlapping with another transfer. In IDLE, the bus is quiet. When a master needs to talk to a peripheral, the bus enters SETUP for exactly one cycle: PADDR (address), PSELx (select), and PWRITE (direction) are all driven, but PENABLE stays low and no data moves yet. On the next clock edge the bus moves to ACCESS and PENABLE goes high; for a write, PWDATA is sampled by the slave; for a read, the slave drives PRDATA. If the slave needs more time it holds PREADY low, stretching ACCESS for as many cycles as needed. Once complete, the bus returns to IDLE, or moves straight into the next SETUP if back-to-back transfers target the same peripheral.
Q3.What does PREADY do in APB, and what happens if a slave never asserts it?
PREADY is the slave's way of telling the master 'I'm not done yet — hold this ACCESS phase open.' As long as PREADY stays low during ACCESS, every other bus signal (address, data, control) remains frozen exactly as it was, and the transfer simply doesn't complete. If a slave design bug or a genuine hardware fault causes PREADY to never assert, the bus hangs indefinitely on that transfer — which is why real systems typically include a bus timeout/watchdog mechanism at the bridge or interconnect level to detect and recover from (or at least flag) a slave that never responds.
Q4.Explain HTRANS in AHB and what each of its four encoded values means.
HTRANS is a 2-bit signal describing the type of the current transfer on the address phase. IDLE (2'b00) means no transfer is happening this cycle — the bus is idle even though a master may still hold the bus. BUSY (2'b01) means the master intends to continue a burst but isn't ready to supply the next address this cycle (a deliberate gap mid-burst). NONSEQ (2'b10) marks the first beat of any single transfer or the first beat of a burst, and the address can be anything. SEQ (2'b11) marks every subsequent beat of a burst, with the address incrementing (or wrapping) according to the burst type established at the start.
Q5.What's the difference between AHB's INCR and WRAP burst types, and why does WRAP matter for cache fills?
INCR bursts simply increment the address by the transfer size on each beat, continuing in a straight line — used for general sequential memory access. WRAP bursts increment the same way but wrap back around to an aligned boundary once they reach the end of the burst length, staying within a fixed-size, aligned address window. WRAP matters for cache line fills because it enables 'critical-word-first' behavior: the specific word the CPU actually stalled waiting for can be fetched first (wherever it falls within the cache line), with the rest of the line wrapping around afterward, letting the CPU resume execution as soon as its specific word arrives instead of waiting for the whole line to fill in a fixed start-to-end order.
Q6.What is AHB's 1KB address boundary rule, and why does a burst transfer need to respect it?
AHB (and AXI) bursts are not allowed to cross a 1KB (or 4KB for AXI) address boundary within a single burst, because many memory controllers and address decoders are organized around fixed-size regions, and a burst that straddled a boundary could span two different slaves or memory banks mid-transfer. The master is responsible for splitting a would-be crossing burst into two separate bursts that each stay within one boundary.
Q7.What is AHB-Lite, and why has it mostly replaced 'full' AHB in real designs?
AHB-Lite is a single-master subset of the full AHB specification that removes the arbitration logic needed to support multiple masters sharing one bus — in full AHB, a central arbiter has to decide which master drives the address/control lines each cycle, which is genuinely complex to design and verify correctly. AHB-Lite assumes exactly one master per bus instance, capturing nearly all of AHB's pipelining performance benefit with dramatically simpler implementation. In modern designs, most system-level arbitration and multi-master interconnect is handled by AXI instead, with AHB-Lite retained as a simpler mid-tier bus connecting a single IP to a bridge.
Q8.Why does AXI use five separate channels instead of one shared bus like AHB?
AXI splits every transaction into five independent channels — write address (AW), write data (W), write response (B), read address (AR), and read data (R) — precisely so reads and writes never have to share a single address or data bus and block each other. Because the channels are fully independent, a master can have a write and a read outstanding simultaneously, and because each channel runs its own VALID/READY handshake, throughput on one channel doesn't stall because of pressure on another. This channel-level parallelism is the fundamental reason AXI scales to the bandwidth requirements of a full SoC interconnect in a way that a single shared bus like AHB or APB structurally cannot.
Q9.Explain the VALID/READY handshake used on every AXI channel.
Every AXI channel uses the same simple two-signal handshake: the source of the information asserts VALID once its data is ready to be transferred, and the destination asserts READY once it's able to accept it. The actual transfer happens on the clock edge where both VALID and READY are high simultaneously; either side is allowed to stall (hold its signal) for as long as needed, and per the AXI spec, once VALID is asserted it must stay asserted (and the data must not change) until the transfer actually completes — a source isn't allowed to 'give up' and change its mind mid-handshake, which is a common protocol compliance bug to check for in AXI verification.
Q10.What are the three burst types in AXI, and how does WSTRB extend write flexibility?
AXI supports FIXED bursts (every beat targets the same address — useful for streaming into or out of a FIFO-mapped register), INCR bursts (standard incrementing sequential access, up to 256 beats in AXI4), and WRAP bursts (wraps back to an aligned boundary, used for critical-word-first cache fills, same concept as AHB's WRAP). WSTRB is a byte-level write-strobe signal accompanying write data, letting a single write beat update only specific byte lanes within the data word rather than the whole word — essential for supporting partial-word or unaligned writes cleanly within a wide data bus without requiring a separate read-modify-write sequence.
Q11.How does AXI achieve out-of-order transaction completion, and why does that matter?
Every outstanding request on the AW or AR channels carries a transaction ID (AWID or ARID), and the corresponding response on the B or R channel echoes that same ID back (BID or RID). This lets a master issue many requests before any of them complete, and lets a slave — or an interconnect fanning requests out to several slaves with very different latencies — return responses in whatever order they actually finish, as long as responses that share the same ID stay in relative order with each other. This matters because it decouples request latency from achievable throughput: a slow request (e.g. to DRAM) doesn't block a fast request behind it (e.g. to a fast SRAM) just because they were issued in a particular order.
Q12.What is AXI4-Lite, and when would you use it instead of full AXI4?
AXI4-Lite is a simplified subset of AXI4 that removes bursting entirely — every transaction is a single, non-burst beat with only one transaction outstanding at a time — while keeping the same five-channel structure and VALID/READY handshake. It's used for simple, low-bandwidth register interfaces (the role APB used to fill exclusively) that still need to sit natively on an AXI-based interconnect, avoiding the need for the interconnect to support multiple different bus protocol standards just to reach a handful of configuration registers.
Q13.Why is AXI verification particularly handshake- and ordering-heavy compared to APB or AHB verification?
Because AXI has five independent channels each running their own VALID/READY handshake, plus ID-based out-of-order completion rules, there are far more ways for a real implementation to subtly violate the protocol: holding VALID without holding data stable, incorrectly reordering responses that share the same ID, deadlocking because a slave's write response channel is blocked waiting on something that itself depends on that response, or violating the required relative ordering between channels for a single transaction. This is why AXI verification IP (VIP) — protocol checkers that continuously monitor every channel for compliance — is a near-universal component of any SoC-level verification environment involving an AXI interconnect.
Q14.How does an AHB-to-APB (or AXI-to-APB) bridge work, and why is it necessary?
A bridge sits between the high-performance bus and the APB peripheral segment, translating the more complex protocol's pipelined, potentially bursting transfers into APB's simple, one-at-a-time, non-pipelined SETUP/ACCESS sequence — buffering the necessary information (address, data, direction) across the translation since APB has no concept of pipelining or bursts at all. It's necessary because dozens of small peripherals (UARTs, timers, GPIO, interrupt controllers) don't need — and would be wasteful to implement with — full AHB or AXI interfaces, but the interconnect still needs one consistent way to reach all of them from the CPU's perspective.
Q15.Qualcomm SoCs use APB, AHB, and AXI for very different jobs — what actually determines which bus a given IP block sits on?
The deciding factors are bandwidth and latency sensitivity. Low-bandwidth control/status registers (UART, GPIO, timers) go on APB, where simplicity and low gate count matter more than speed. Moderate-bandwidth blocks that still fit on one shared bus (some DMA engines, mid-tier peripherals) sit on AHB (almost always AHB-Lite). High-bandwidth blocks that need parallelism and outstanding transactions — CPU clusters, GPU, memory controllers — sit on AXI, usually through a full AXI-based interconnect fabric.
Q16.Why is APB the natural choice for something like a UART or GPIO controller, but a poor choice for a DDR memory controller?
APB's non-pipelined, one-transfer-at-a-time protocol keeps its gate count and timing closure trivial, which is ideal when the block behind it (a UART, GPIO bank, or timer) will never need more than a few register accesses per second. A DDR controller needs to sustain gigabytes per second with many outstanding requests in flight — APB's strictly sequential, no-pipelining structure would make it the bottleneck of the entire chip, which is exactly the bandwidth AXI is designed to support instead.
Q17.What's the difference between AHB's single shared bus with an external arbiter, and AXI's approach to multiple masters?
Classic (non-Lite) AHB has one shared address/data bus with an external arbiter granting bus ownership to one master at a time each cycle — genuinely complex to implement correctly, which is why most designs today use AHB-Lite (single master, no arbiter) instead. AXI handles multiple masters by giving each one its own independent set of channels into an interconnect fabric, which arbitrates and routes transactions to slaves — masters don't share a single bus at all, which is what lets multiple transactions from different masters actually overlap in time.