DigiFlop

Make sure faulty chips can be caught later.

Chip Design Flow · Design for Test (DFT)
Design for Test (DFT)
Make sure faulty chips can be caught later.

Extra logic — scan chains — is stitched into the netlist so flip-flops can be tested after manufacturing. This lets automated test equipment detect fabrication defects on every single chip produced.

InputsGate-level netlist
OutputsScan-inserted netlist, test patterns (ATPG)
Typical toolsScan insertion & ATPG tools
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