Digital Design Fundamentals

A complete, structured digital logic design course -- from number systems and Boolean algebra through K-map minimization, combinational circuit design, latches and flip-flops, counters and registers, and finite state machines. 43 lessons, each with detailed explanations, worked examples, and clean diagrams.

Full curriculum -- 43 lessons

• Introduction to Digital Systems
  Analog vs digital, why digital is noise-immune, and how the course is structured.
• Number Systems: Introduction and Radix Conversion
  Decimal, binary, octal, hexadecimal -- positional weight and fast conversion techniques both ways.
• Complements of Number Systems: 1's and 2's Complement
  How binary subtraction is done with adder hardware, using 1's and 2's complement.
• 9's/10's, 7's/8's and 15's/16's Complements
  The same complement idea generalized to decimal, octal and hexadecimal.
• Logic Gates, Truth Tables, and Why NAND Beats NOR
  The basic gate set, their truth tables, and the CMOS transistor-level reason NAND is preferred over NOR.
• NAND and NOR Realization of Basic Gates
  Building NOT, AND and OR gates using only NAND (or only NOR) gates -- and why that matters in real chip design.
• SOP and POS Forms: Minterms, Maxterms, Canonical Forms
  Minterms, maxterms, and writing any truth table as canonical Sum-of-Products or Product-of-Sums.
• Boolean Equations and Switching Equations
  The algebraic laws (identity, absorption, consensus, De Morgan's) used to simplify logic expressions by hand.
• Boolean Minimization and K-Maps (2, 3, 4 Variables) + Logisim
  Why K-maps work (Gray code adjacency), building 2/3/4-variable maps, grouping rules, and getting started in Logisim.
• Implicants: PI, EPI, NEPI and RPI
  The vocabulary for classifying K-map groupings and the step-by-step method for picking the true minimum expression.
• K-Maps with 5 and 6 Variables
  Extending K-maps beyond 4 variables using multiple overlaid grids, and why the technique doesn't scale further.
• K-Maps with Don't-Care Conditions
  Using undefined/impossible input combinations (X) to your advantage for a smaller, simpler circuit.
• Building Combinational Logic Circuits: Code Converters
  The full design flow (truth table -> K-map -> SOP -> gates), applied to BCD-to-Excess-3 conversion.
• Code Converters (Continued): Binary/Gray and Excess-3/BCD
  Binary<->Gray code (the XOR-chain pattern) and Excess-3<->BCD, reinforcing the design flow with two more worked examples.
• Arithmetic Circuits: Half Adder, Full Adder, Parallel Adder
  HA and FA truth tables/equations, building a FA from two HAs, and chaining FAs into a ripple-carry parallel adder.
• Subtractors: Half Subtractor, Full Subtractor, and Using Complements
  HS/FS equations, and the standard trick of reusing adder hardware for subtraction via 2's complement.
• MSI Circuits: Multiplexers, and Building Gates from a MUX
  What a MUX is, its SOP structure, building larger MUXes from smaller ones, and using a 2:1 MUX to realize basic gates.
• Boolean Function Implementation Using a MUX
  Implementing any truth table directly with a full-size MUX, and the size-saving (n-1)-variable reduced method.
• Full Adder Using MUX, and MUX Trees
  Building a full adder purely from 4:1 MUXes, and the general MUX-tree pattern for larger selectors.
• Demultiplexers
  The DEMUX as the functional opposite of a MUX -- truth table, equations, and its close relationship to a decoder.
• Decoders
  How a decoder activates exactly one output per input code, active-high vs active-low, and building larger decoders from smaller ones.
• Decoder Configurations and Priority Encoders
  Cascading decoders using enable inputs, memory address decoding, and the priority encoder (used in interrupt controllers).
• Comparators
  1-bit and multi-bit magnitude comparators, the MSB-first cascading logic, and chaining comparator ICs for wider numbers.
• Introduction to Sequential Logic Circuits: The NOR Latch
  Combinational vs sequential logic, feedback, and the basic 1-bit storage element -- the cross-coupled NOR SR latch.
• The NAND Latch
  Cross-coupled NAND gates as the active-low dual of the NOR latch, and when each style is used in real design.
• Clocked SR, D, JK, T Latches and the Racing Problem
  Adding a clock to gate latch inputs, the D/JK/T variants that fix the SR forbidden state, and why level-sensitive latches can race.
• Master-Slave Combination and Edge-Triggered Flip-Flops
  How master-slave construction tames the racing problem, what edge-triggering means, and why it became the modern standard.
• Revision: SR, D, JK, T Latches, and Worked Timing Examples
  A side-by-side comparison table for all four latch types, plus a fully worked step-by-step timing trace.
• Master-Slave Combination: Its Limitations
  Why master-slave construction fixes racing for SR/D/T but leaves JK vulnerable to the race-around problem.
• Edge-Triggering and Its Advantages
  Why edge-triggered flip-flops eliminate racing entirely and became the default building block of modern synchronous design.
• Asynchronous Inputs, Characteristic Equations and Excitation Tables
  Preset/Clear overriding inputs, the characteristic equation for each flip-flop type, and excitation tables for sequential design.
• Flip-Flop Conversions
  The general excitation-table method for implementing any flip-flop type using any other type, worked for JK<->D.
• Applications of Flip-Flops: Asynchronous Up/Down Counters
  Building a ripple counter by chaining toggle flip-flops, and how using Q vs Q' gives you up-counting vs down-counting.
• Asynchronous Mod-N Counters
  Building non-power-of-2 counters using the asynchronous-clear (detect-and-reset) technique, worked for Mod-6.
• Async Up/Down Counters: Timing Considerations and Limitations
  How propagation delay accumulates ('rippling') across stages, and why this caps speed and causes decoding glitches.
• Design of Synchronous Counters
  The general 5-step synchronous design procedure, worked fully for a 3-bit binary up counter using T flip-flops.
• Registers, Shift Registers, and the Universal Shift Register
  What a register is, the 4 standard shift register I/O configurations, and building a mode-selectable universal shift register.
• Counters Based on Shift Registers: Ring and Johnson Counters
  Feedback-wired shift registers as counters -- straight feedback gives a Ring counter, inverted feedback gives a Johnson counter.
• Frequency Divider Circuits
  Why a toggle flip-flop is a divide-by-2 circuit, chaining for divide-by-2^n, and Mod-N counters for arbitrary divide ratios.
• Frequency Multiplier Circuits and Edge Detectors
  Why true frequency multiplication needs a PLL (not just flip-flops), and how to build a single-cycle edge-detector pulse.
• Introduction to Finite State Machines: Implicit and Explicit FSM
  What an FSM is, how it generalizes everything from latches through counters, and implicit vs explicit description styles.
• FSM Sequence Detector: Mealy and Moore Models
  Building an overlapping-'11' sequence detector both ways, and the full Mealy vs Moore comparison this problem is designed to teach.
• Problems on FSM: Worked Sequence Detector Designs
  Three fully worked sequence-detector problems -- overlapping, non-overlapping, and multi-pattern detection with shared states.