CDC Interview Preparation

40 real-world CDC interview questions, reconstructed and organized into 4 sections: fundamentals, synchronization techniques, verification methodology, and advanced topics (NoC, coherence protocols, DDR PHY). Every answer is detailed, with clean diagrams and tables where they make the concept click faster than text alone -- plus two short video walkthroughs for the trickiest ideas.

Section 1: CDC Fundamentals

• Q1. What exactly is a clock domain crossing, and why does it carry real risk?
• Q2. What is metastability, physically, and exactly when does it occur?
• Q3. What does MTBF mean for a synchronizer, and what does each term in the formula actually represent?
• Q4. Walk through exactly what a two-flip-flop synchronizer does, with a timing diagram showing sync1, sync2, and the resolution window.
• Q5. Why does a synchronizer need at least 2 flip-flops instead of just 1, and how many stages do the highest-reliability design tiers (military/space) actually use?
• Q6. What actually makes one flip-flop a better choice than another for use as a synchronizer stage?
• Q7. What's fundamentally different — and fundamentally harder — about crossing a multi-bit bus versus a single bit?
• Q8. What's the real difference between a CDC crossing and a timing constraint like set_false_path — and why is confusing them dangerous?
• Q9. What are the main categories of CDC failure modes that a design review should be watching for?
• Q10. How does CDC show up differently at the full SoC level, once you add multiple power domains and clock gating into the picture?

Section 2: Synchronization Techniques

• Q11. How does a pulse synchronizer work, and when is it the right tool to reach for?
• Q12. Give a full architecture overview of an async FIFO for multi-bit CDC — where do wptr and rptr actually live, and what crosses the boundary?
• Q13. Why must async FIFO pointers specifically use gray code, and what does 'only 1 bit changes' actually buy you?
• Q14. How do you actually calculate the right depth for an async FIFO given a specific CDC interface's traffic pattern?
• Q15. What is meant by a bus encoding synchronizer, and why is one-hot encoding not automatically safer than binary for CDC?
• Q16. What's the difference between an open-loop and a closed-loop enable synchronizer, and how do you decide which one a design needs?
• Q17. How do you correctly synchronize a reset signal across a clock domain — why assert asynchronously but release synchronously?
• Q18. What special precautions does a fast-to-slow clock domain crossing need that a same-speed crossing doesn't?
• Q19. Going the other direction — slow source into a fast destination — is a plain 2-flop synchronizer still enough?
• Q20. What happens at a CDC boundary when the source domain is power-gated, and what do isolation cells actually do about it?

Section 3: CDC Verification

• Q21. At a mechanical level, how does a CDC lint tool like SpyGlass CDC actually find and classify crossings?
• Q22. What's the real difference between structural and functional CDC analysis, and why do you need both?
• Q23. What are the common violation categories a CDC lint tool reports, and what does it actually mean to waive a path correctly?
• Q24. Since ordinary simulation can't model metastability, how do teams actually simulate CDC behavior for extra confidence?
• Q25. What does 'clock domain identification' mean in CDC analysis, and why is it harder than it sounds?
• Q26. What is a CDC reconvergence path (W_MASYNC), and why is it one of the hardest CDC bug classes to catch?
• Q27. What does a proper verification plan for an async FIFO actually look like — functional checks plus formal, specifically?
• Q28. What does a real CDC sign-off flow look like end to end, from clock ID through final waiver review?
• Q29. How does CDC analysis handle generated clocks — dividers, gated clocks, PLL outputs — differently from ordinary primary clocks?
• Q30. What's the specific CDC risk when integrating third-party black-box IP, and how do teams actually handle it?

Section 4: Advanced CDC

• Q31. What is token-based synchronization, and how does it solve CDC for complex multi-field data that a simple handshake can't handle cleanly?
• Q32. How does CDC get handled in a Network-on-Chip, where packets are constantly moving between many independently-clocked tiles?
• Q33. In a large multi-clock SoC with many contributing teams, who should actually own CDC verification, and why does it matter?
• Q34. Why exactly does a correctly-synchronized CDC path still need to be false-pathed in timing constraints, and what breaks if you skip that step?
• Q35. What specific CDC challenges come up when a clock's source can dynamically switch through a clock mux?
• Q36. How do you analyze whether an async FIFO's throughput and latency are actually good enough for a given interface, and when does the added latency become a real problem?
• Q37. How does clock domain crossing interact with a cache coherence protocol like ACE or CHI — specifically, how do snoop responses safely cross domains?
• Q38. Walk through a concrete real-world example: how does read data cross from the PHY clock domain into the system clock domain in a DDR memory interface?
• Q39. What do 'same-edge' and 'opposite-edge' launch-capture actually mean in a CDC-adjacent timing context, and when does that distinction stop being meaningful?
• Q40. Pulling it all together: what's a genuinely complete CDC sign-off checklist look like before you'd approve a design for tapeout?